This invention relates to switching networks which interconnect a plurality of accessing circuits and a plurality of peripheral circuits and more particularly to an arrangement for preventing simultaneous connections by two or more of the accessing circuits to any one of the peripheral circuits.
The use of individual peripheral devices by a number of using devices is well known in the prior art. For example, a plurality of processor circuits may access a plurality of memory circuits. Of course, a using device can access a peripheral device only if the required peripheral device is not busy servicing another using device. A variety of prior art arrangements assign priorities to the various using devices and access is controlled in accordance with the established priorities. Where priorities are inappropriate, for example where few conflicts occur or relatively short holding times are required, a simpler busy test arrangement is provided, commonly referred to as a busy bus. In prior art busy test arrangements, a using device requiring connection to a given peripheral device connects to the peripheral device and tests the busy bus to determine the busy/idle status of that device. If an idle condition exists, the using circuit seizes the peripheral device and makes it busy. Unfortunately, in such prior art busy bus schemes, there is a short period of time before a peripheral circuit is made busy during which period of time two or more using devices can gain access to the peripheral circuit and be simultaneously connected to it. Such simultaneous connections are undesirable at best and are intolerable in many applications.